This application claims priority under 35 USC §119 to Korean Patent Application No. 2006-01287, filed on Jan. 5, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to generating a reset signal, and more particularly, to generating a reset signal with minimized range of a tripping voltage with temperature variation for stable operation of a semiconductor device.
2. Background of the Invention
Applying a power supply voltage to operate a semiconductor device such as a semiconductor memory device is referred to as “power-up”. The semiconductor memory device does not operate immediately at the moment when the power supply voltage is applied. The power supply voltage typically ramps up, and the semiconductor memory device operates after the level of the power supply voltage reaches a predetermined level.
Thus, a semiconductor memory device has a circuit for preventing unstable operation when the logic level is uncertain or preventing latch-up effect during power-up. Typically, a reset signal generating circuit in the semiconductor memory device generates a reset signal used to reset devices of the semiconductor memory device until the power supply voltage is stabilized, and to complete the reset operation when the power supply voltage is stabilized. The reset signal may be called a power-up reset signal, and the reset signal generating circuit may be called a power-up reset circuit.
FIG. 1 is a circuit diagram of a conventional reset signal generating circuit. Referring to FIG. 1, the conventional reset signal generating circuit includes a level sensing unit 10 and a plurality of inverters 12, 14 and 16. The level sensing unit is for sensing a level of a power supply voltage VDD. The inverters 12, 14, and 16 are for buffering a level sense signal output from the level sensing unit 10 and for generating a reset signal VCCHB.
The level sensing unit 10 includes an NMOSFET (N-channel metal oxide semiconductor field effect transistor) NM10. A gate and a drain of the NMOSFET NM10 are coupled together such that the NMOSFET NM10 is diode-connected. The power supply voltage VDD is applied on the gate and the drain of the NMOSFET NM10. A source of the NMOSFET NM10 is coupled to an output node N10. A resistor R10 is coupled between the output node N10 and a ground node.
The inverter 12 includes a PMOSFET (P-channel metal oxide semiconductor field effect transistor) PM12 and an NMOSFET NM12 having gates coupled together at the output node N10. The source of the PMOSFET PM12 has the power supply voltage VDD applied thereon, and the source of the NMOSFET NM12 is coupled to the ground node. The drains of the PMOSFET PM12 and the NMOSFET NM12 are coupled together at a node N12 forming an output of the inverter 12.
The output of the inverter 12 is coupled as an input to the inverter 14. The configuration of the inverters 14 and 16 are similar to that of the inverter 12. The reset signal generated in FIG. 1 may be from one of the inverters 12, 14, and 16. The output of the inverter 14 is an inverted signal of the output of the inverter 12, and thus is represented as VCCH when the reset signal VCCHB is generated as the output of the inverter 16.
Operation of the reset signal generating circuit of FIG. 1 is now described in reference to FIGS. 2A and 2B. The power supply voltage VDD when initially applied increases gradually typically as a ramp. The NMOSFET NM10 is initially turned off when the power supply voltage VDD is less than a threshold voltage of the NMOSFET NM10 such that the output node N10 is initially at a logic low state. Thus, the PMOSFET PM12 is initially turned on such that the node N12 and thus the reset signal VCCHB initially follow the power supply voltage VDD.
FIG. 2A illustrates voltages at nodes of the reset signal generating circuit of FIG. 1 as the power supply voltage VDD ramps up during power-up. Graphs g11 and g12 are for a voltage level VN10 of the output node N10 of the level sensing unit 10 for variable temperatures. A graph g1 is for the reset signal VCCHB, and a graph gT indicates a trip voltage level of the inverter 12.
As the power supply voltage VDD increases, the reset signal VCCHB initially follows the power supply voltage VDD until a trip point P1 when the power supply voltage VDD reaches a tripping voltage. At the trip point P1, the reset signal VCCHB decreases and maintains a ground voltage level.
FIGS. 2A, 2B, and 3 illustrate just the power-up time period when the power supply voltage VDD increases. However, the power supply voltage VDD eventually reaches and maintains a constant final power supply voltage level after the power-up.
FIG. 2B shows a graph g2 of the voltage signal VCCH output by the inverter 14. As the power supply voltage VDD increases, the voltage signal VCCH is initially at the ground level until the trip point P1. After the trip point P1, the voltage signal VCCH increases to follow the power supply voltage VDD.
Referring to the reset signal generating circuit of FIG. 1 and FIGS. 2A and 2B, the power supply voltage VDD increases to reach the threshold voltage of the NMOSFET NM10. At that point, the NMOSFET NM10 operates as a diode, and the resistor R10 determines the current level flowing through the turned on NMOSFET NM10.
The power supply voltage VDD continues to increase until the voltage at the output node N10 reaches a threshold voltage of the NMOSFET NM12. At that point, the voltage at the output node N12 of the inverter 12 is at the ground voltage level. Herein, the voltage that turns on the NMOSFET NM12 may be called a trip voltage, and the reset signal VCCHB decreases and maintains the ground voltage at such a trip voltage (i.e. point P1 in FIG. 2A). At such a point P1, the voltage signal VCCH output from the inverter 14 increases from the ground voltage level to follow the power supply voltage VDD, as shown in FIG. 2B.
For mobile products having low operating voltages, the trip point is desired to be lowered. Further referring to FIGS. 2A and 2B, the trip point may be lowered to P2 from P1 by adjusting characteristics of the level sensing unit 10. In that case, the voltage at the output node N10 of the level sensing unit 10 follows the graph g11 instead of the graph g12. For example, a resistance of the resistor R10 or transistor characteristics of the NMOSFET NM10 may be so adjusted.
However, lowering such a trip point results in reduced margin of the trip voltage as illustrated by the reduced range T1 in FIG. 2A. Nevertheless, the operation of the reset signal generating circuit of FIG. 1 is sensitive to temperature as illustrated in FIG. 3.
FIG. 3 illustrates the reset signal VCCHB at various temperatures. In FIG. 3, a graph g3 in FIG. 3 indicates the reset signal VCCHB at a hot temperature, a graph g4 indicates the reset signal VCCHB at a normal temperature, and a graph g5 designates the reset signal VCCHB at cold temperature. The hot temperature is higher than the normal temperature, and the cold temperature is lower than the normal temperature. For example, the normal temperature is 25° C., the hot temperature is 100° C., and the cold temperature is −25° C. FIG. 3 illustrates the range of the trip point for the various temperatures.
If the reset signal generating circuit of FIG. 1 is designed for normal temperature, the shift in the trip voltage may be outside of the desired operating margin at high or low temperatures. Thus, a reset signal generator with minimized sensitivity to temperature is desired.